IP PortfolioInterface PHYsstorage_phy
of_sas_phy
SAS 24G PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
SAS-4 PHY at up to 22.5 Gbaud with 20-bit FFE training, OOB signalling and SATA compatibility.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | differential pair | 4 | |
| rx | in | differential pair | 4 | |
| refclk | in | differential pair | 1 | |
| pma_tx | in | parallel | 160 | |
| pma_rx | out | parallel | 160 |
Standards
- SAS-4 (INCITS 534)
More in storage_phy
| ID | Block | Maturity |
|---|---|---|
| of_sata_phy | SATA 6 Gb/s PHY | planned |