IP PortfolioInterface PHYsstorage_phy
of_sata_phy
SATA 6 Gb/s PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
SATA PHY at 1.5, 3 and 6 Gb/s with OOB signalling (COMINIT/COMWAKE), SSC, and PIPE-style interface.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | differential pair | 1 | |
| rx | in | differential pair | 1 | |
| refclk | in | differential pair | 1 | |
| pma_tx | in | parallel | 40 | |
| pma_rx | out | parallel | 40 |
Standards
- Serial ATA Revision 3.5
More in storage_phy
| ID | Block | Maturity |
|---|---|---|
| of_sas_phy | SAS 24G PHY | planned |