IP PortfolioInterface PHYsoptical_phy
of_ring_tuning_ctrl
Micro-ring resonance tuning controller
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
Closed-loop wavelength locking for micro-ring modulators and filters using monitor photodiode ADCs and heater DACs with dither-based control.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| mon_pd | in | analog | 8 | |
| heater | out | analog | 8 |
Standards
No external standard applies.
More in optical_phy
| ID | Block | Maturity |
|---|---|---|
| of_vcsel_driver | VCSEL driver array | planned |
| of_pd_tia | Photodiode TIA array | planned |
| of_sipho_mod_driver | Silicon photonics modulator driver | planned |
| of_cpo_engine_if | Co-packaged optics electrical interface | planned |
| of_lpo_linear_frontend | Linear pluggable optics driver and TIA | planned |
| of_pam4_optical_dsp | PAM4 optical module DSP PHY | planned |