IP PortfolioInterface PHYsoptical_phy
of_cpo_engine_if
Co-packaged optics electrical interface
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
Host-side electrical PHY and management for co-packaged optical engines, with XSR SerDes lanes, laser source control and optical engine telemetry.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | differential pair | 8 | |
| rx | in | differential pair | 8 | |
| par_tx | in | parallel | 1024 | |
| par_rx | out | parallel | 1024 | |
| refclk | in | differential pair | 1 |
Standards
- OIF CEI-112G-XSR
More in optical_phy
| ID | Block | Maturity |
|---|---|---|
| of_vcsel_driver | VCSEL driver array | planned |
| of_pd_tia | Photodiode TIA array | planned |
| of_sipho_mod_driver | Silicon photonics modulator driver | planned |
| of_ring_tuning_ctrl | Micro-ring resonance tuning controller | planned |
| of_lpo_linear_frontend | Linear pluggable optics driver and TIA | planned |
| of_pam4_optical_dsp | PAM4 optical module DSP PHY | planned |