IP PortfolioInterface PHYsmipi_phy
of_mipi_dphy
MIPI D-PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 1
MIPI D-PHY transmitter and receiver with 1 to 4 data lanes plus clock lane, HS and LP modes, deskew calibration and PPI interface for CSI-2 and DSI.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| data | inout | differential pair | 4 | |
| clk_lane | inout | differential pair | 1 | |
| ppi_tx | in | parallel | 64 | |
| ppi_rx | out | parallel | 64 | |
| refclk | in | clock | 1 |
Standards
- MIPI D-PHY v3.0
More in mipi_phy
| ID | Block | Maturity |
|---|---|---|
| of_mipi_cphy | MIPI C-PHY | planned |
| of_mipi_dcphy | MIPI D-PHY/C-PHY combo | planned |
| of_mipi_mphy | MIPI M-PHY | planned |
| of_mipi_aphy | MIPI A-PHY | planned |
| of_slvs_ec_phy | SLVS-EC receiver PHY | planned |