IP PortfolioInterface PHYsmipi_phy
of_slvs_ec_phy
SLVS-EC receiver PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
Embedded-clock SLVS-EC receiver PHY with CDR per lane for high-speed image sensors.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| rx | in | differential pair | 8 | |
| par_rx | out | parallel | 80 | |
| refclk | in | clock | 1 |
Standards
- SLVS-EC v2.0
More in mipi_phy
| ID | Block | Maturity |
|---|---|---|
| of_mipi_dphy | MIPI D-PHY | planned |
| of_mipi_cphy | MIPI C-PHY | planned |
| of_mipi_dcphy | MIPI D-PHY/C-PHY combo | planned |
| of_mipi_mphy | MIPI M-PHY | planned |
| of_mipi_aphy | MIPI A-PHY | planned |