IP PortfolioInterface PHYsmemory_buffer
of_ddr5_db
DDR5 data buffer
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
DDR5 LRDIMM and MRDIMM data buffer that retimes and isolates the DQ/DQS interface between host and DRAM, with training support and BCOM control port.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| mdq | inout | parallel | 8 | |
| mdqs | inout | differential pair | 1 | |
| dq | inout | parallel | 8 | |
| dqs | inout | differential pair | 1 | |
| bcom | in | parallel | 4 |
Standards
- JEDEC JESD79-5
More in memory_buffer
| ID | Block | Maturity |
|---|---|---|
| of_ddr5_rcd | DDR5 registering clock driver | planned |