IP PortfolioInterface PHYsmemory_buffer
of_ddr5_rcd
DDR5 registering clock driver
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
DDR5 RDIMM registering clock driver that re-drives command/address and clocks to two subchannels with parity checking and loopback, available as an IP block for custom modules.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| dca | in | parallel | 14 | |
| dck | in | differential pair | 1 | |
| qca | out | parallel | 56 | |
| qck | out | differential pair | 4 |
Standards
- JEDEC JESD82-511
- JEDEC JESD79-5
Notes
Building block for the Dyber, Inc. memory module; MRDIMM MRCD variant follows the JEDEC MRDIMM standard.
More in memory_buffer
| ID | Block | Maturity |
|---|---|---|
| of_ddr5_db | DDR5 data buffer | planned |