IP PortfolioInterface controllersethernet_offload
of_udp_ip_offload
UDP/IPv4 offload engine
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Hardware UDP/IP stack with ARP cache, ICMP echo, IPv4 header checksum and UDP port demultiplexing to AXI-Stream user ports.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| mac_tx | out | AXI4-Stream | 64 | |
| mac_rx | in | AXI4-Stream | 64 | |
| udp_tx | in | AXI4-Stream | 64 | |
| udp_rx | out | AXI4-Stream | 64 |
Standards
- IETF RFC 768
- IETF RFC 791
- IETF RFC 826
Basis projects
Permissive open projects the implementation may build on.
- verilog-ethernet (MIT)
- LiteEth (BSD-2-Clause)
More in ethernet_offload
| ID | Block | Maturity |
|---|---|---|
| of_eth_ptp_tsu | IEEE 1588 PTP timestamping unit | simulated |
| of_tcp_offload | TCP offload engine | planned |
| of_roce_v2 | RoCE v2 RDMA engine | planned |
| of_uet_transport | Ultra Ethernet transport engine | planned |
| of_macsec_framer | MACsec SecTAG framer | planned |
| of_ncsi | NC-SI sideband controller | planned |