IP PortfolioInterface controllersethernet_offload
of_eth_ptp_tsu
IEEE 1588 PTP timestamping unit
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Precision Time Protocol hardware clock with one-step and two-step timestamp insertion, frequency and offset adjustment, PPS and periodic outputs.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| ts_tx | out | valid-qualified bus | 96 | |
| ts_rx | out | valid-qualified bus | 96 | |
| pps_out | out | serial | 1 |
Standards
- IEEE 1588-2019
Basis projects
Permissive open projects the implementation may build on.
- verilog-ethernet (MIT)
More in ethernet_offload
| ID | Block | Maturity |
|---|---|---|
| of_udp_ip_offload | UDP/IPv4 offload engine | planned |
| of_tcp_offload | TCP offload engine | planned |
| of_roce_v2 | RoCE v2 RDMA engine | planned |
| of_uet_transport | Ultra Ethernet transport engine | planned |
| of_macsec_framer | MACsec SecTAG framer | planned |
| of_ncsi | NC-SI sideband controller | planned |