IP PortfolioInterface controllersethernet_switch
of_eth_l2_switch
Layer-2 Ethernet switch
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Multi-port store-and-forward Ethernet switch with MAC learning table, VLAN (802.1Q), per-port priority queues, IGMP snooping and port mirroring.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| port_rx | in | AXI4-Stream | 256 | |
| port_tx | out | AXI4-Stream | 256 |
Standards
- IEEE 802.1Q-2022