of_static_mem_ctrl

Static memory controller (SRAM/NOR/PSRAM)

Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2

Asynchronous and page-mode external bus controller for SRAM, parallel NOR flash and async PSRAM with per-chip-select timing registers.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
addr	out	parallel	26
data	inout	parallel	16
ctl	out	parallel	8

Standards

No external standard applies.

More in sram

ID	Block	Maturity
of_qdr_sram_ctrl	QDR-II+/QDR-IV SRAM controller	planned