of_qdr_sram_ctrl

QDR-II+/QDR-IV SRAM controller

Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3

Controller for QDR-II+ and QDR-IV synchronous SRAM with separate read and write ports, burst-of-2/4 modes, read latency calibration and parity.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
host	in	AXI4-Stream	128
addr	out	parallel	22
dq_w	out	parallel	72
dq_r	in	parallel	72

Standards

No external standard applies.

More in sram

ID	Block	Maturity
of_static_mem_ctrl	Static memory controller (SRAM/NOR/PSRAM)	planned