IP PortfolioInterface controllerspsram
of_hyperbus
HyperBus controller
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
HyperBus memory controller for HyperRAM and HyperFlash with DDR transfers, RWDS handling, variable latency and AXI memory-mapped access.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| ck | out | differential pair | 1 | |
| cs_n | out | parallel | 2 | |
| dq | inout | parallel | 8 | |
| rwds | inout | serial | 1 |
Standards
- HyperBus Specification (Infineon)