IP PortfolioInterface controllersspi
of_spi_slave
SPI slave
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
SPI peripheral-mode block with mode 0 to 3 support and register-mapped transmit and receive data.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| sclk | in | clock | 1 | |
| mosi | in | serial | 1 | |
| miso | out | serial | 1 | |
| cs_n | in | serial | 1 |
Standards
No external standard applies.
More in spi
| ID | Block | Maturity |
|---|---|---|
| of_spi_master | SPI master | fpga-routed |