IP PortfolioInterface controllersspi
of_spi_master
SPI master
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
SPI controller with programmable clock polarity, phase, divider and chip select.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| sclk | out | clock | 1 | |
| mosi | out | serial | 1 | |
| miso | in | serial | 1 | |
| cs_n | out | parallel | 4 |
Standards
No external standard applies.
More in spi
| ID | Block | Maturity |
|---|---|---|
| of_spi_slave | SPI slave | simulated |