IP PortfolioInterface controllersspi_flash
of_qspi_flash
Quad SPI NOR flash controller
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Single, dual and quad SPI NOR flash controller with memory-mapped execute-in-place reads over AXI, SFDP discovery, command sequencer for program and erase, and DMA.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| sclk | out | clock | 1 | |
| cs_n | out | parallel | 2 | |
| io | inout | parallel | 4 |
Standards
- JEDEC JESD216
Basis projects
Permissive open projects the implementation may build on.
- LiteSPI (BSD-2-Clause)
Notes
AXI4 memory-mapped XIP port is part of the full implementation.
More in spi_flash
| ID | Block | Maturity |
|---|---|---|
| of_xspi_octal | Octal SPI / xSPI controller | planned |