IP PortfolioInterface controllersspace_avionics
of_spacefibre
SpaceFibre interface
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
SpaceFibre lane, data link and network layers with virtual channels, quality of service, retry and broadcast messages over a SerDes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| phy_tx | out | parallel | 40 | |
| phy_rx | in | parallel | 40 | |
| tx | in | AXI4-Stream | 32 | |
| rx | out | AXI4-Stream | 32 |
Standards
- ECSS-E-ST-50-11C
More in space_avionics
| ID | Block | Maturity |
|---|---|---|
| of_spacewire | SpaceWire codec and router port | planned |
| of_mil1553 | MIL-STD-1553B controller | planned |
| of_arinc429 | ARINC 429 transceiver controller | planned |
| of_afdx_es | AFDX (ARINC 664 Part 7) end system | planned |