IP PortfolioInterface controllersspace_avionics
of_afdx_es
AFDX (ARINC 664 Part 7) end system
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Avionics full-duplex switched Ethernet end system with virtual link scheduling by bandwidth allocation gap, redundancy management and integrity checking.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| mac_a | out | AXI4-Stream | 8 | |
| mac_b | out | AXI4-Stream | 8 | |
| rx_a | in | AXI4-Stream | 8 | |
| rx_b | in | AXI4-Stream | 8 |
Standards
- ARINC 664 Part 7
More in space_avionics
| ID | Block | Maturity |
|---|---|---|
| of_spacewire | SpaceWire codec and router port | planned |
| of_spacefibre | SpaceFibre interface | planned |
| of_mil1553 | MIL-STD-1553B controller | planned |
| of_arinc429 | ARINC 429 transceiver controller | planned |