IP PortfolioInterface controllersi2c
of_smbus_pmbus
SMBus/PMBus controller
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
SMBus host and target with packet error checking (PEC), SMBALERT#, clock-low and bus timeouts, ARP and PMBus command decoding for power management.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| smbclk | inout | serial | 1 | |
| smbdat | inout | serial | 1 | |
| smbalert_n | inout | serial | 1 |
Standards
- SMBus 3.2
- PMBus 1.3.1
More in i2c
| ID | Block | Maturity |
|---|---|---|
| of_i2c_master | I2C master | fpga-routed |
| of_i2c_slave | I2C slave | simulated |
| of_i2c_multimaster | I2C multi-master controller | simulated |