IP PortfolioInterface controllersi3c
of_i3c_controller
MIPI I3C controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
MIPI I3C primary controller with SDR and HDR-DDR modes, dynamic address assignment, in-band interrupts, hot-join and legacy I2C device support.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| scl | inout | serial | 1 | |
| sda | inout | serial | 1 |
Standards
- MIPI I3C v1.1.1
- MIPI I3C HCI v1.1
More in i3c
| ID | Block | Maturity |
|---|---|---|
| of_i3c_target | MIPI I3C target | planned |