IP PortfolioInterface controllersi2c
of_i2c_multimaster
I2C multi-master controller
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
I2C controller and target in one block with multi-master arbitration, 10-bit addressing, Hs-mode up to 3.4 Mbit/s, general call, FIFOs and DMA handshake.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| scl | inout | serial | 1 | |
| sda | inout | serial | 1 |
Standards
- NXP UM10204 I2C-bus specification Rev. 7.0
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
- verilog-i2c (MIT)
More in i2c
| ID | Block | Maturity |
|---|---|---|
| of_i2c_master | I2C master | fpga-routed |
| of_i2c_slave | I2C slave | simulated |
| of_smbus_pmbus | SMBus/PMBus controller | planned |