IP PortfolioInterface controllersspi_flash
of_xspi_octal
Octal SPI / xSPI controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Octal SPI controller for xSPI NOR flash and PSRAM with SDR and DTR transfers, data strobe capture, XIP read cache and on-the-fly command profiles.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| sclk | out | clock | 1 | |
| cs_n | out | parallel | 2 | |
| io | inout | parallel | 8 | |
| dqs | inout | serial | 1 |
Standards
- JEDEC JESD251
- JEDEC JESD216
More in spi_flash
| ID | Block | Maturity |
|---|---|---|
| of_qspi_flash | Quad SPI NOR flash controller | simulated |