IP PortfolioInterface controllersethernet_pcs
of_eth_usxgmii
USXGMII multi-rate PCS
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
USXGMII PCS for 10M to 10G multi-rate copper PHY attachment with symbol replication and in-band auto-negotiation over a 10.3125 Gb/s SerDes lane.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| serdes_tx | out | parallel | 64 | |
| serdes_rx | in | parallel | 64 | |
| xgmii_tx | in | parallel | 72 | |
| xgmii_rx | out | parallel | 72 |
Standards
No external standard applies.
Notes
Defined by the Cisco USXGMII specification; cite the revision when sourced.
More in ethernet_pcs
| ID | Block | Maturity |
|---|---|---|
| of_eth_sgmii_pcs | SGMII / 1000BASE-X PCS | planned |
| of_eth_flexe | FlexE shim | planned |