IP PortfolioInterface controllersethernet_mac
of_eth_mac_10g
10G Ethernet MAC and 10GBASE-R PCS
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 1
10 Gbit/s MAC with XGMII and 64b/66b 10GBASE-R PCS including scrambler, block lock and BER monitor, plus optional Clause 74 BASE-R FEC.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| serdes_tx | out | parallel | 64 | |
| serdes_rx | in | parallel | 64 | |
| tx | in | AXI4-Stream | 64 | |
| rx | out | AXI4-Stream | 64 |
Standards
- IEEE 802.3-2022
Basis projects
Permissive open projects the implementation may build on.
- verilog-ethernet (MIT)
More in ethernet_mac
| ID | Block | Maturity |
|---|---|---|
| of_eth_mac_1g | 1G Ethernet MAC | simulated |
| of_eth_mac_25g | 25G Ethernet MAC, PCS and RS-FEC | planned |
| of_eth_mac_100g | 40G/50G/100G Ethernet MAC and PCS | planned |
| of_eth_mac_400g | 200G/400G Ethernet MAC and PCS | planned |
| of_eth_mac_800g | 800G Ethernet MAC and PCS | planned |