IP PortfolioInterface controllersethernet_pcs
of_eth_sgmii_pcs
SGMII / 1000BASE-X PCS
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
8b/10b PCS with Clause 37 and SGMII auto-negotiation, rate adaptation for 10/100/1000 and a TBI interface to a SerDes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| tbi_tx | out | parallel | 10 | |
| tbi_rx | in | parallel | 10 | |
| gmii_tx | in | parallel | 10 | |
| gmii_rx | out | parallel | 10 |
Standards
- IEEE 802.3-2022
- Cisco SGMII 1.8
Basis projects
Permissive open projects the implementation may build on.
- verilog-ethernet (MIT)
More in ethernet_pcs
| ID | Block | Maturity |
|---|---|---|
| of_eth_usxgmii | USXGMII multi-rate PCS | planned |
| of_eth_flexe | FlexE shim | planned |