IP PortfolioInterface controllersfieldbus

of_iolink_master

IO-Link master port

Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3

IO-Link master port controller with COM1/COM2/COM3 rates, wake-up generation, M-sequence handling and SIO fallback.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAPB control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
cq_txoutserial4 
cq_rxinserial4 
cq_enoutparallel4 

Standards

  • IEC 61131-9
  • IO-Link Interface and System Specification V1.1.3

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