IP PortfolioInterface controllerscxl
of_cxl_root_port
CXL host root port
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Host-side CXL root port with CXL.io/.cache/.mem, home agent request handling, HDM decoding and interleave across expanders.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pipe_tx | out | parallel | 512 | |
| pipe_rx | in | parallel | 512 | |
| host_req | in | AXI4-Stream | 512 | |
| host_rsp | out | AXI4-Stream | 512 |
Standards
- CXL 2.0
- CXL 3.1
More in cxl
| ID | Block | Maturity |
|---|---|---|
| of_cxl11_dev | CXL 1.1 device controller | planned |
| of_cxl2_type3 | CXL 2.0 Type 3 memory expander controller | planned |
| of_cxl3_dev | CXL 3.x device controller | planned |
| of_ccix | CCIX transaction and link layer | planned |