IP PortfolioInterface controllerscxl
of_cxl2_type3
CXL 2.0 Type 3 memory expander controller
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
CXL 2.0 Type 3 device controller for memory expansion with CXL.mem, HDM decoders, multi-logical-device support, poison and media error reporting and a back-end memory request port.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pipe_tx | out | parallel | 512 | |
| pipe_rx | in | parallel | 512 | |
| mem_req | out | AXI4-Stream | 512 | |
| mem_rsp | in | AXI4-Stream | 512 |
Standards
- CXL 2.0
- PCI Express Base 5.0
Notes
Primary CXL attach for the Dyber, Inc. III-V memory bridge die.
More in cxl
| ID | Block | Maturity |
|---|---|---|
| of_cxl11_dev | CXL 1.1 device controller | planned |
| of_cxl3_dev | CXL 3.x device controller | planned |
| of_cxl_root_port | CXL host root port | planned |
| of_ccix | CCIX transaction and link layer | planned |