of_ccix

CCIX transaction and link layer

Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3

CCIX cache-coherent interconnect layers carried over PCIe with request agent, home agent and slave agent message handling.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
tlp_tx	out	AXI4-Stream	512
tlp_rx	in	AXI4-Stream	512

Standards

CCIX Base Specification 1.1

Notes

CCIX is largely superseded by CXL; kept for legacy Arm server interop.

More in cxl

ID	Block	Maturity
of_cxl11_dev	CXL 1.1 device controller	planned
of_cxl2_type3	CXL 2.0 Type 3 memory expander controller	planned
of_cxl3_dev	CXL 3.x device controller	planned
of_cxl_root_port	CXL host root port	planned