IP PortfolioInterface controllerscan
of_can20
CAN 2.0 controller
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Classical CAN controller with standard and extended identifiers, acceptance filters, TX priority buffers, error confinement counters and bus-off recovery.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| can_tx | out | serial | 1 | |
| can_rx | in | serial | 1 |
Standards
- ISO 11898-1:2015
- Bosch CAN 2.0