IP PortfolioPhysical IPdie marking, alignment and finishing
of_seal_ring
Seal ring
Maturity plannedTargets ASIC (CMOS) onlyDifficulty EasyPriority 1
Multi-layer guard ring with stacked vias and corner stress relief protecting the die edge from cracks and moisture, with optional RF-cut gaps.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
No external standard applies.
More in die marking, alignment and finishing
| ID | Block | Maturity |
|---|---|---|
| of_align_marks | Lithography alignment and overlay marks | planned |
| of_die_mark | Die marking and logo cells | planned |
| of_chip_id_rom | Metal-programmable chip ID cell | planned |
| of_fill_gen | Density fill generator | planned |