IP PortfolioPhysical IPtest structures and process monitors
of_rel_struct
Reliability test structures
Maturity plannedTargets ASIC (CMOS) onlyDifficulty MediumPriority 2
Electromigration lines, via chains, gate oxide TDDB capacitors and hot-carrier transistor arrays for wafer-level reliability qualification.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| probe | inout | analog | 16 |
Standards
- JEDEC JESD61
- JEDEC JESD92
More in test structures and process monitors
| ID | Block | Maturity |
|---|---|---|
| of_matching_arrays | Device matching test arrays | planned |
| of_pcm_si | Silicon process control monitor set | planned |
| of_ring_osc | Ring oscillator process monitor | planned |
| of_sram_yield | SRAM yield and bitmap test vehicle | planned |
| of_thermal_test | Thermal test structures | planned |
| of_crack_detect | Die crack and moisture detector | planned |