IP PortfolioPhysical IPtest structures and process monitors
of_matching_arrays
Device matching test arrays
Maturity plannedTargets ASIC (CMOS) onlyDifficulty MediumPriority 3
Addressable arrays of transistors, resistors and capacitors in common-centroid and distance-varied layouts for mismatch (Pelgrom) characterization.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| probe | inout | analog | 8 |
Standards
No external standard applies.
More in test structures and process monitors
| ID | Block | Maturity |
|---|---|---|
| of_pcm_si | Silicon process control monitor set | planned |
| of_ring_osc | Ring oscillator process monitor | planned |
| of_rel_struct | Reliability test structures | planned |
| of_sram_yield | SRAM yield and bitmap test vehicle | planned |
| of_thermal_test | Thermal test structures | planned |
| of_crack_detect | Die crack and moisture detector | planned |