IP PortfolioDatapath and DSPbit manipulation
of_prienc
Priority encoder
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Priority encoder with one-hot grant, binary index and valid; LSB- or MSB-first priority.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| req | in | parallel | 32 | |
| idx | out | parallel | 5 |
Standards
No external standard applies.
More in bit manipulation
| ID | Block | Maturity |
|---|---|---|
| of_lzc | Leading-zero / leading-one counter | fpga-routed |
| of_popcount | Population count | simulated |
| of_shifter | Barrel shifter / rotator | simulated |
| of_bitrev | Bit, byte and nibble reverse / swap | planned |
| of_bitmanip_rv | RISC-V bit-manipulation unit | planned |
| of_clmul | Carry-less multiplier | planned |