IP PortfolioDatapath and DSPbit manipulation
of_bitmanip_rv
RISC-V bit-manipulation unit
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Execution unit for the RISC-V Zba, Zbb, Zbc and Zbs extensions: shifted add, count leading/trailing zeros, popcount, rotates, min/max, carry-less multiply and single-bit ops.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| opnd | in | parallel | 128 | |
| y | out | parallel | 64 |
Standards
- RISC-V Bit-Manipulation ISA-extensions 1.0.0
More in bit manipulation
| ID | Block | Maturity |
|---|---|---|
| of_lzc | Leading-zero / leading-one counter | fpga-routed |
| of_popcount | Population count | simulated |
| of_prienc | Priority encoder | simulated |
| of_shifter | Barrel shifter / rotator | simulated |
| of_bitrev | Bit, byte and nibble reverse / swap | planned |
| of_clmul | Carry-less multiplier | planned |