IP PortfolioDatapath and DSPbit manipulation
of_clmul
Carry-less multiplier
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
GF(2) polynomial multiplier returning the full 2n-bit carry-less product, with optional reduction modulo a configurable polynomial.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| a | in | parallel | 64 | |
| b | in | parallel | 64 | |
| y | out | parallel | 128 |
Standards
No external standard applies.
More in bit manipulation
| ID | Block | Maturity |
|---|---|---|
| of_lzc | Leading-zero / leading-one counter | fpga-routed |
| of_popcount | Population count | simulated |
| of_prienc | Priority encoder | simulated |
| of_shifter | Barrel shifter / rotator | simulated |
| of_bitrev | Bit, byte and nibble reverse / swap | planned |
| of_bitmanip_rv | RISC-V bit-manipulation unit | planned |