IP PortfolioDatapath and DSPdsp transforms and oscillators
of_nco
NCO / direct digital synthesizer
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Phase-accumulator oscillator with sine/cosine LUT or CORDIC output, phase dithering, run-time frequency and phase offset, and phase-continuous retuning.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| m_out | out | AXI4-Stream | 32 |
Standards
No external standard applies.
More in dsp transforms and oscillators
| ID | Block | Maturity |
|---|---|---|
| of_fft_stream | Streaming pipelined FFT/IFFT | planned |
| of_fft_mem | Memory-based mixed-radix FFT | planned |
| of_cordic | CORDIC rotator and vectoring unit | fpga-routed |
| of_window | Window function generator | planned |
| of_dct | 2D DCT / IDCT | planned |