IP PortfolioDatapath and DSPdsp transforms and oscillators

of_cordic

CORDIC rotator and vectoring unit

Maturity fpga-routedTargets FPGA + ASICDifficulty MediumPriority 1

Iterative or pipelined CORDIC in rotation and vectoring modes (circular, linear, hyperbolic) for sin/cos, atan2, magnitude, phase and coordinate rotation.

FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.

Interfaces

PortDirectionKindWidthNotes
s_ininAXI4-Stream48 
m_outoutAXI4-Stream48 

Standards

No external standard applies.

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