IP PortfolioDatapath and DSPdsp signal processing
of_ddc
Digital down-converter
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Configurable DDC chain combining NCO mixer, CIC decimator, compensation FIR and half-band stages for multiple channels.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| s_in | in | AXI4-Stream | 16 | |
| m_out | out | AXI4-Stream | 32 |
Standards
No external standard applies.
More in dsp signal processing
| ID | Block | Maturity |
|---|---|---|
| of_cmul | Complex multiplier | simulated |
| of_mixer | Digital complex mixer | planned |
| of_duc | Digital up-converter | planned |
| of_correlator | Multi-lag correlator | planned |
| of_matched_filter | Matched filter and pulse compressor | planned |
| of_agc | Digital automatic gain control | planned |