IP PortfolioDatapath and DSPdsp signal processing
of_correlator
Multi-lag correlator
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Streaming auto- and cross-correlation over a configurable number of lags with integration and dump, for synchronization and preamble detection.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| s_in | in | AXI4-Stream | 32 | |
| ref | in | AXI4-Stream | 32 | |
| m_out | out | AXI4-Stream | 64 |
Standards
No external standard applies.