IP PortfolioVerification IPopen bus vip
of_vip_wb_bfm
Wishbone bus functional model and agent
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Wishbone master and slave agents for classic and pipelined modes with randomized acknowledge and stall timing.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| m_wb | out | valid-qualified bus | 72 | |
| s_wb | in | valid-qualified bus | 72 |
Standards
- Wishbone B4
Notes
Implemented as of_vip_wb_master and of_vip_wb_slave (classic mode; no pipelined mode yet).
More in open bus vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_wb_mon | Wishbone monitor and protocol checker | simulated |
| of_vip_tilelink_mon | TileLink monitor and protocol checker | planned |
| of_vip_tilelink_bfm | TileLink bus functional model and agent | planned |
| of_vip_obi_mon | OBI monitor and protocol checker | planned |
| of_vip_obi_bfm | OBI bus functional model and agent | planned |