IP PortfolioVerification IPopen bus vip
of_vip_tilelink_mon
TileLink monitor and protocol checker
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
TileLink monitor for TL-UL, TL-UH and TL-C checking channel handshakes, opcode and parameter legality, source ID reuse and burst beat counts.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 256 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- SiFive TileLink 1.8
More in open bus vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_wb_mon | Wishbone monitor and protocol checker | simulated |
| of_vip_wb_bfm | Wishbone bus functional model and agent | simulated |
| of_vip_tilelink_bfm | TileLink bus functional model and agent | planned |
| of_vip_obi_mon | OBI monitor and protocol checker | planned |
| of_vip_obi_bfm | OBI bus functional model and agent | planned |