IP PortfolioVerification IPmipi vip
of_vip_dphy_mon
MIPI D-PHY monitor and checker
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
D-PHY lane monitor checking high-speed entry and exit sequences, LP state transitions, escape mode and timing parameters on clock and data lanes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| lane | in | differential pair | 5 | |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- MIPI D-PHY
More in mipi vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_csi2_mon | MIPI CSI-2 monitor and protocol checker | planned |
| of_vip_csi2_bfm | MIPI CSI-2 camera model and agent | planned |
| of_vip_dsi_mon | MIPI DSI monitor and protocol checker | planned |
| of_vip_dsi_bfm | MIPI DSI bus functional model and agent | planned |
| of_vip_cphy_mon | MIPI C-PHY monitor and checker | planned |