IP PortfolioSoC interconnectmonitoring and error reporting
of_ras_reri
RAS error record unit (RERI)
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Error record banks for reporting corrected and uncorrected hardware errors with severity, address and syndrome, signalling via interrupts.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| err_in | in | valid-qualified bus | 64 |
Standards
- RISC-V RERI 1.0
More in monitoring and error reporting
| ID | Block | Maturity |
|---|---|---|
| of_axi_perfmon | AXI4 performance monitor | planned |
| of_hpm_counters | Hardware event counter bank | planned |
| of_bus_timeout | Bus transaction timeout monitor | planned |