IP PortfolioSoC interconnectmonitoring and error reporting
of_hpm_counters
Hardware event counter bank
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Bank of 64-bit counters selecting from hundreds of system events with overflow interrupts, start/stop triggers and snapshot.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| events | in | parallel | 256 |
Standards
No external standard applies.
More in monitoring and error reporting
| ID | Block | Maturity |
|---|---|---|
| of_axi_perfmon | AXI4 performance monitor | planned |
| of_ras_reri | RAS error record unit (RERI) | planned |
| of_bus_timeout | Bus transaction timeout monitor | planned |