IP PortfolioSoC interconnectamba interconnect
of_axi4_qos
AXI4 QoS regulator
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Per-master bandwidth and outstanding-transaction regulator that throttles AW/AR issue to programmed rates and sets AxQOS for downstream arbitration.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| s_axi | in | valid-qualified bus | 256 | AXI4 slave port (AW/W/AR channels) |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
- AMBA AXI4
More in amba interconnect
| ID | Block | Maturity |
|---|---|---|
| of_axil_xbar | AXI4-Lite crossbar | fpga-routed |
| of_axis_arb | AXI4-Stream packet arbiter / mux | simulated |
| of_axis_fifo | AXI4-Stream FIFO | simulated |
| of_axis_reg_slice | AXI4-Stream register slice | simulated |
| of_axis_width_conv | AXI4-Stream width converter | simulated |
| of_axi4_xbar | AXI4 crossbar | simulated |
| of_axi4_reg_slice | AXI4 register slice | simulated |
| of_axi4_width_conv | AXI4 data-width converter | simulated |
| of_axi4_id_remap | AXI4 ID width converter | planned |
| of_axi4_burst_split | AXI4 burst splitter | planned |