AXI4-Lite crossbar

Maturity fpga-routedTargets FPGA + ASICDifficulty MediumPriority 1

N x M AXI4-Lite crossbar (32-bit data) with base/mask address decoding, an internal DECERR slave for unmapped addresses, independent read and write paths and per-slave round-robin arbitration (of_arb_rr); transactions to different slaves run in parallel.

FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
s_axil	in	valid-qualified bus	128
m_axil	out	valid-qualified bus	128

Standards

AMBA AXI4-Lite

More in amba interconnect

ID	Block	Maturity
of_axis_arb	AXI4-Stream packet arbiter / mux	simulated
of_axis_fifo	AXI4-Stream FIFO	simulated
of_axis_reg_slice	AXI4-Stream register slice	simulated
of_axis_width_conv	AXI4-Stream width converter	simulated
of_axi4_xbar	AXI4 crossbar	simulated
of_axi4_reg_slice	AXI4 register slice	simulated
of_axi4_width_conv	AXI4 data-width converter	simulated
of_axi4_id_remap	AXI4 ID width converter	planned
of_axi4_burst_split	AXI4 burst splitter	planned
of_axi4_firewall	AXI4 firewall	simulated