IP PortfolioSecurityanti_tamper
of_sec_zeroize
Zeroisation controller
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Ordered erasure of key registers, crypto state and selected SRAM on tamper or command, with completion status that survives reset.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| zeroize_req | in | serial | 1 |
Standards
- NIST FIPS 140-3
More in anti_tamper
| ID | Block | Maturity |
|---|---|---|
| of_sec_vglitch_det | Voltage glitch detector | planned |
| of_sec_clk_monitor | Clock glitch and frequency monitor | planned |
| of_sec_laser_det | Laser fault injection detector | planned |
| of_sec_temp_tamper | Temperature tamper detector | planned |
| of_sec_timing_sensor | Timing violation sensors | planned |
| of_sec_active_shield | Active shield mesh | planned |
| of_sec_alert_handler | Security alert handler | simulated |
| of_sec_em_fi_det | Electromagnetic fault injection detector | planned |