IP PortfolioSecurityanti_tamper
of_sec_clk_monitor
Clock glitch and frequency monitor
Maturity plannedTargets ASIC (CMOS) onlyDifficulty MediumPriority 1
Delay-line and reference-counter monitor that detects clock glitches, stops and out-of-range frequencies.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| mon_clk | in | clock | 1 | |
| alert | out | serial | 1 |
Standards
- NIST FIPS 140-3
More in anti_tamper
| ID | Block | Maturity |
|---|---|---|
| of_sec_vglitch_det | Voltage glitch detector | planned |
| of_sec_laser_det | Laser fault injection detector | planned |
| of_sec_temp_tamper | Temperature tamper detector | planned |
| of_sec_timing_sensor | Timing violation sensors | planned |
| of_sec_active_shield | Active shield mesh | planned |
| of_sec_alert_handler | Security alert handler | simulated |
| of_sec_zeroize | Zeroisation controller | planned |
| of_sec_em_fi_det | Electromagnetic fault injection detector | planned |